Duration
30h Th, 20h Pr, 40h Proj.
Number of credits
| Master of Science (MSc) in Biomedical Engineering | 5 crédits | |||
| Master of Science (MSc) in Electrical Engineering | 5 crédits |
Lecturer
Language(s) of instruction
English language
Organisation and examination
Teaching in the second semester
Schedule
Units courses prerequisite and corequisite
Prerequisite or corequisite units are presented within each program
Learning unit contents
Theory, design and simulation of standard integrated circuits (analogue and digtial). Technology involved in creating CMOS. Basic functions and building blocks. Performance evaluation. System design methods. Switched capacitor and sample and hold circuits circuits. Filters. A/D converters. Noise in analogue circuits.
Learning outcomes of the learning unit
At the end of the course, students will master the bases of integrated CMOS circuit design.
Prerequisite knowledge and skills
ELEN0040
Planned learning activities and teaching methods
Lectures, tutorials, logic function SPICE simulation and VHDL FPGA programming.
Mode of delivery (face-to-face ; distance-learning)
Face-to-face lectures, tutorials, independent laboratory work.
Recommended or required readings
Slides.
Carusone, Johns, Martin, "Analog Integrated Circuit Design", Wiley, 2011.
Assessment methods and criteria
Written examination (60%)
Written report of the lab project (40%)
Work placement(s)
Organizational remarks
Contacts
Jean-Michel Redouté
jean-michel.redoute@uliege.be
Adaptation of teaching commitments following the COVID-19 pandemic for the May-June 2020 session
Teaching methods implemented : distance-learning
The lecture slides, lecture recordings, TP descriptions and solutions are available on this website.
The project presentation will be replaced by a remote evaluation: kindly refer here below for more information.
Assessment subjects
The exam will cover the content that we have seen during the lectures and the practical sessions (TPs). The exam will consist of:
1) a theoretical part (multiple choice questions).
2) an exercise part (multiple choice questions and open questions requiring a short answer).
The project presentation will be replaced by an evaluation: to this end, please send Hervé and Gabriel per email, by Friday the 15th of May, the following three items:
1) a report describing the project (max 10 pages, 5 is optimal).
2) a short and basic video (no need for fancy stuff) made by one of the group members (5-10 minutes) to explain very briefly what the FPGA code is doing, how we should run the program, and how the objectives set out at the onset have been achieved.
3) the FPGA code (please use comments where needed so as to make this readable)
Allow me to emphasize the need to work on this project remotely, i.e. sharing code online. Also, please do not integrate / foresee extra hardware to work on top of the original FPGA board you have received (as we would not be able to run your code on our boards otherwise).
The marks distribution for this unit is similar to what has been mentioned originally: 40% project / 60% exam. The exam mark distribution will be 50% theory and 50% exercises.
Assessment methods
Refer to here above.
Contacts
Jean-Michel Redouté
jean-michel.redoute@uliege.be
Adaptation of teaching commitments following the COVID-19 pandemic for the Aug-Sept 2020 session
Assessment subjects
The exam will cover the content that we have seen during the lectures and the practical sessions (TPs). The exam will consist of:
1) a theoretical part (multiple choice questions).
2) an exercise part (multiple choice questions and open questions requiring a short answer).
Please log in on eCampus at 9am on Wednesday the 2nd of September to start the exam.
For completing the project, please send Hervé and Gabriel per email, by Friday the 14th of August, the following three items:
1) a report describing the project (max 10 pages, 5 is optimal).
2) a short and basic video (no need for fancy stuff) made by one of the group members (5-10 minutes) to explain very briefly what the FPGA code is doing, how we should run the program, and how the objectives set out at the onset have been achieved.
3) the FPGA code (please use comments where needed so as to make this readable)
Allow me to emphasize the need to work on this project remotely, i.e. sharing code online. Also, please do not integrate / foresee extra hardware to work on top of the original FPGA board you have received (as we would not be able to run your code on our boards otherwise).
The marks distribution for this unit is similar to what has been mentioned originally: 40% project / 60% exam. The exam mark distribution will be 50% theory and 50% exercises.
Assessment methods
Refer to here above.
Contacts
Jean-Michel Redouté
jean-michel.redoute@uliege.be